Saving Moore’s Law With High-k Materials

It has been more than 4 decades, but Moore’s Law is still relevant and the leading semi-conductor companies, along with their suppliers, are moving forward with breakthrough advancements in materials, processes and fabrication technologies. I was quite fascinated by some of these developments as I read the cover story in the July 9, 2007 issue of C&E News. There is tremendous excitement about “high-k” (high dielectric constant) materials for their potential use as transistor gate insulators in semi-conductor chips.

Early this year, Intel announced the successful commercial development of a 45-nm transistors using new high-k materials and metal gates. The current state-of-the art process is the 65 nm process which Intel uses in the current generation of Core(TM) and Core2 microprocessors. Commercial production for the 45-nm transistors is on track for the second half of 2007 in Fab 32 at Ocotillo, Arizona (under construction) and Fab 28 in Israel (first half of 2008). IBM and Advanced Micro Devices have also announced similar plans for first quarter of 2008.

Silicon dioxide is currently used as the gate insulator material (k=4.2). Shrinking chip size forces the gate oxide layer to be thinner, which has now been reduced to below 2 nm in the current transistors. At this level, chip performance is compromised due to electron leakage across the thin gate insulator. According to Intel’s press release, transistor gate leakage associated with the ever-thinning gate dielectric made of SiO2 has been recognized by the industry as one of the most formidable technical challenges facing Moore’s Law in this decade.

Hafnium based high-k materials provide a solution to this problem by allowing a thicker layer of the gate insulator to be used in the transistor which solves the leakage problem and facilitates high performance. However, before this technology can be implemented, two associated problems need to be solved:

• A suitable precursor which can be applied on silicon using an appropriate technique that can be integrated with the current process, and;
• A metal-based gate electrode which can replace the currently used polysilicon material

Intel seems to have solved both of these problems, however the specific details of the materials and process recipe are trade secrets. Here is a sketch of their High-k + Metal Gate Transistor:

Excellent details are provided in a presentation by Mark Bohr, a Senior Fellow in Intel’s Logic Technology and Development Group.

Texas Instrument has provided a glimpse of this technology by disclosing that their high-k material in SoC processors for wireless products will be hafnium silicon oxynitride (HfSiON), which is formed by depositing hafnium silicon oxide and then reacting it with nitrogen plasma. Here is an excerpt from their press release, which highlights the success of this technology:

Through a modular addition to the typical CMOS gate stack process, HfSiON integration has been demonstrated offering mobility that is 90 percent of the silicon dioxide universal mobility curve, with effective oxide thicknesses (EOTs) below 1-nm. These results were accomplished without sacrificing reliability or adding significant cost to the CMOS process. Precise tuning of the film composition, tight controls, and high throughput also make HfSiON suitable for high volume manufacturing.

Hafnium oxide has a dielectric constant of about 30, however it is a challenging material to integrate into a silicon-based semiconductor. HfSiON seems to be a good compromise material although the dielectric constant is lower. We can expect to see continued development of these materials to optimize the balance of performance and large scale manufacturability.